Mismatch Reduction in an On-Chip Image Processing Chip
Performing Feature Detection
Ania Mitros, Christof Koch

Feature extraction is a first step for many existing computer vision algorithms. This computation is also often one of the most time- and resource-intensive steps because the same local computation must be performed at each pixel. To head towards a real-time, small-size, energy-efficient implementation, Pesavento implemented the Tomasi- Kanade feature extraction algorithm in silicon. Although each feature detector worked splendidly, transistor mismatch killed the performance of the array. I have been re-implementing the blocks of the feature detector with floating gate transistors within each to permanently program away the mismatch. I have implemented mismatch reduction in the photoreceptor and the multiplier; both are tested and function as desired.

CMOS Imager with Embedded Analog Early Image Processor
Christophe Basset, Bedabrata Pain (JPL), Pietro Perona

Abstract. We are developing a computational CMOS imager with integrated early image processing general-purpose filter. The goal of this collaborative work with the Jet Propulsion Laboratory is to produce a single chip serving as a camera able to pre-process the image in real-time through a filter chosen by the user, allowing an efficient implementation of a variety of computationally intensive applications such as autonomous navigation, object avoidance or intercept, real-time target tracking and recognition. (full report)